Independent control of stacked electronic modules

ABSTRACT

Apparatus and methods are disclosed to allow independent control of stacked memory modules. In one embodiment, an apparatus may comprise first, second, and third modules, each of the first, second and third modules having a plurality of stacked memory dice, at least some of the plurality of stacked memory dice including a Chip Enable (CE) signal electrically accessible from a bottom surface of a corresponding module of the first, second and third modules. The apparatus may comprise a Package-on-Package (PoP) structure where the first, second and third modules are attached to one another such that an individual access to each CE signal associated with the PoP structure is provided from the bottom surface of the corresponding module.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.14/615,896, filed Feb. 6, 2015, which is a continuation of U.S.application Ser. No. 13/493,744, filed Jun. 11, 2012, now issued as U.S.Pat. No. 8,952,515, which is a continuation of U.S. application Ser. No.12/463,329, filed May 8, 2009, now issued as U.S. Pat. No. 8,198,717,all of which are incorporated herein by reference in their entirety.

BACKGROUND INFORMATION

Die stacking integrates semiconductor devices vertically in a singlepackage in order to directly influence the amount of silicon that can beincluded in a given package footprint. Die stacking simplifies thesurface-mount pc-board assembly and conserves pc-board real estatebecause fewer components are placed on the board. Die stacking hasincluded different memory combinations that place flash memory with SRAMand RAM. Die stacking has evolved to multiple die stacks andside-by-side combinations of stacked and unstacked dies within apackage.

The dies are mounted on a substrate which may then be bumped to createeither a Chip Scale Package (CSP) or a Ball Grid Array (BGA) as thefinal package. Present die stacking techniques include mounting smallerdies onto larger ones to enable wire bonding of both, as well astechniques for stacking same-size die. To further increase the memorydensity and memory bandwidth available in a given size footprint,Package-on-Package (PoP) may be utilized to vertically connect multiplepackages such as a logic package with a memory package, where eachpackage may contain one or more die. Still, improvements in packagingare needed as the number of stacked-die in a package is expanded.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed outand distinctly claimed in the concluding portion of the specification.The invention, however, both as to organization and method of operation,together with objects, features, and advantages thereof, may best beunderstood by reference to the following detailed description when readwith the accompanying drawings in which:

FIG. 1 is an embodiment of a wireless device connected to mass storagehaving Phase-Change Memory (PCM) in vertically interconnected multipleidentical memory packages in a cube architecture in accordance with thepresent invention;

FIG. 2 illustrates a die-stacking module having vias in the mold andChip Enable signals shifted to new locations as these signals pass fromthe top of the vias, through the package substrate and down to thesolder balls in accordance with the present invention;

FIG. 3 illustrates a die-stacking module using a laminated board toprovide electrical connections and Chip Enable signals shifted to newlocations as these signals pass from the top of the vias, through thepackage substrate and down to the solder balls in accordance with thepresent invention;

FIG. 4 illustrates a plurality of die-stacking modules in aPackage-On-Package assembly in accordance with the present invention;and

FIG. 5 is a bottom view of the Package-On-Package assembly that providesa separate Chip Enable for each memory die in the package in accordancewith the present invention.

It will be appreciated that for simplicity and clarity of illustration,elements illustrated in the figures have not necessarily been drawn toscale. For example, the dimensions of some of the elements may beexaggerated relative to other elements for clarity. Further, whereconsidered appropriate, reference numerals have been repeated among thefigures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the invention.However, it will be understood by those skilled in the art that thepresent invention may be practiced without these specific details. Inother instances, well-known methods, procedures, components and circuitshave not been described in detail so as not to obscure the presentinvention.

Use of the terms “coupled” and “connected”, along with theirderivatives, may be used. It should be understood that these terms arenot intended as synonyms for each other. Rather, in particularembodiments, “connected” may be used to indicate that two or moreelements are in direct physical or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are ineither direct or indirect (with other intervening elements between them)physical or electrical contact with each other, and/or that the two ormore elements co-operate or interact with each other (e.g. as in a causeand effect relationship).

In one embodiment, an apparatus may comprise first, second, and thirdmodules, each of the first, second and third modules having a pluralityof stacked memory dice, at least some of the plurality of stacked memorydice including a Chip Enable (CE) signal electrically accessible from abottom surface of a corresponding module of the first, second and thirdmodules. The apparatus may comprise a PoP structure where the first,second and third modules are attached to one another such that anindividual access to each CE signal associated with the PoP structure isprovided from the bottom surface of the corresponding module. Variousembodiments are described below with respect to FIGS. 1-5.

The wireless architecture embodiment illustrated in FIG. 1 shows asystem 10 that includes a processor that communicates with a massstorage device 24 in accordance with the present invention. System 10may include one or more antennas to allow a radio to communicate withother over-the-air communication devices. As such, system 10 may operatein wireless networks such as, for example, Wireless Fidelity (Wi-Fi)that provides the underlying technology of Wireless Local Area Network(WLAN) based on the IEEE 802.11 specifications, WiMax and Mobile WiMaxbased on IEEE 802.16-2005, or close proximity Bluetooth technology,although the present invention is not limited to operate in only thesenetworks. The radio subsystems collocated in the same platform of system10 may provide the capability of communicating with different frequencybands in an RF/location space with other devices in a network. It shouldbe understood that the scope of the present invention is not limited bythe types, the number, or the frequency of the communication protocolsthat may be used by system 10.

The embodiment illustrates the coupling of an antenna structure to atransceiver 12 to accommodate modulation/demodulation. In general,analog front end transceiver 12 may be a stand-alone Radio Frequency(RF) discrete or integrated analog circuit, or transceiver 12 may beembedded with a processor 20 having one or more processor cores 16 and18. The multiple cores allow processing workloads to be shared acrossthe cores and handle baseband functions and application functions. Dataand instructions may transfer through an interface 22 between theprocessor and memory storage in mass storage device 24.

Mass storage device 24 may include both volatile and nonvolatilememories. Many wireless applications in mobile products have stringentpackaging constraints that need a reduced footprint for at least aportion of the memory in the mass storage device 24. In accordance withthe present invention, the mass storage device incorporates bothdie-stacking and a Package-On-Package technology 410.

FIG. 2 illustrates eight memories stacked one on top of another, withwire bonds providing electrical connections from pads on the substrateof the memory die to pad sites located on a surface of the packagesubstrate. Although the figure shows eight memory dice in die-stackingmodule 26, it should be understood that this number of memory die is notlimiting to the present invention and other embodiments may encompass adifferent number of memory die. The embodiment illustrates independentlycontrolling the die within each package of a PoP structure by providinga unique Chip Enable (CE) signal at the bottom of the PoP memorystructure. The embodiment shows shifting the CE signal within identicalpackages in the PoP memory structure for example, but the technique maybe used for stacking die-on-die, or any plurality of memory modules.

The different embodiments for die-stacking module 26 include a varietyof nonvolatile memory technologies. One embodiment incorporatesnonvolatile memory having a phase change material. The Phase ChangeMemory (PCM) may be referred to as a Phase-Change Random Access Memory(PRAM or PCRAM), Ovonic Unified Memory (OUM) or Chalcogenide RandomAccess Memory (C-RAM). The arrays of PCM cells include alloys ofelements of group VI of the periodic table, elements such as Te or Sethat are referred to as chalcogenides or chalcogenic materials. Thechalcogenide cells may be used advantageously to provide data retention,where the data remains stable even after the power is removed from thenonvolatile memory. Taking the phase change material as Ge₂Sb₂Tes forexample, two phases or more are exhibited having distinct electricalcharacteristics useful for memory storage.

In another embodiment the nonvolatile memories in die-stacking module 26may be Magnetic Random Access Memory (MRAM) cells. In these cellsmagnetic storage elements are formed from two ferromagnetic plates (notshown) located at an intersection of a row and column line and selectedby a Magnetic Tunnel Junction (MTJ) device (not shown). Current impartedto the row line in one direction causes a magnetic field operative onthe MRAM cell biasing the MRAM cell toward a binary state. Due to amagnetic tunnel effect, the electrical resistance of the memory cellchanges based on the orientation of the fields in the two plates.

In yet another embodiment the nonvolatile memory arrays in die-stackingmodule 26 may be Ferroelectric Random Access Memory (FRAM) cells. Thetransistor-capacitor cell (not shown) includes the ferroelectricmaterial where a bi-stable atom is shifted to form two stablepolarization states. Memory cell data may be written by positively ornegatively orienting the dipoles of the ferroelectric material via anapplied polarizing voltage. Read control circuitry senses the directionof the stable electric polarization that remains in place even after theelectric field is removed.

With reference to FIG. 2, the bond pads on each memory die arepreferably located along one edge of the die, or alternatively, locatedon the top surface on opposing sides of the die. Limits on the bond siteplacements facilitate access by a wire bonding tool to the pads for downbonding to a surface of the package substrate. Placement of memory diein the stacking process calls for one die to be placed on top of anotherwith or without spacers separating the die. The figure shows diestacking without the use of separators or spacers, and further shows thedie being stair-stepped to prevent physical contact of a die to the bondwires of the die below it. Although the figure shows every other diebeing stair-stepped, any number of die may be stair-stepped beforerepeating. Further, the stacking process may also include rotating eachsuccessively placed memory die by 90 degrees or 180 degrees relative tothe previous memory die in the stack. Thus, to facilitate wire bondingcapabilities in stacking multiple devices in a Ball Grid Array (BGA)surface mount module, decisions may be based on the bond pad placementsas designed on the memory die to determine any need for separators, thestacking order, the thickness of the memory die substrates, and theirstair-stepping and die rotation configurations.

FIG. 2 also shows upper connections 204, 206 on the top of a packagesubstrate 202 extended vertically through a package mold 216 to createelectrical pads 212, 214 on the top of the die-stacking module 26. Theconnection may be completed by drilling vias 208, 210 into the mold andthen filling the vias with a solder paste, electrically conductiveadhesives, or other suitable electrically conductive materials.Alternatively, solder or metal pillars may be in place prior to the moldprocess, where a grinding process on the finished mold exposes the metalfor the electrical pads 212, 214.

In accordance with the present invention, the CE signals, such as thechip enable signal for the top die 218, may be down bonded from a bondpad on the memory die to the package substrate, where an interconnecttrace signal 220 electrically routes that CE to one of the upperconnections on the package substrate 202 that is further electricallyconnected to a solder ball such as, for example, solder ball 222. Insome embodiments the CE signals from the various memory die may be keptseparate. Thus, with eight memory die in die-stacking module 26 thereare eight CE signals, with each CE signal accessible through a separatesolder ball. However, in other embodiments one or more of the CE signalsmay be combined through trace signals in the package substrate 202, andthus, fewer than eight CE signals made available through the solderballs.

Note that the CE signals in each die-stacking module 26 are shiftedbetween the bottom solder balls and the top lands. By way of example,electrical pad 212 is not connected to the solder ball 222 that liesbeneath that pad, but rather, electrical pad 212 is shifted by tracesignal 201 in package substrate 202 to electrically connect to solderball 224. Similarly, electrical pad 214 is not connected to the solderball 224 that lies beneath that pad, but rather, electrical pad 214 isalso shifted by a trace to electrically connect to solder ball 226.

FIG. 3 illustrates another embodiment that utilizes a laminated board230 to provide a connection between upper connection 204 on the packagesubstrate 202 and the electrical pad 212 on the top of die-stackingmodule 26. In addition, laminated board 230 provides connections betweenupper connection 206 and electrical pad 214, and so forth. Thus,laminated board 230 provides a plurality of electrical connectionsbetween the top of the package substrate 202 and the top of thedie-stacking module 26. While the figure shows a vertical connection inthe laminated board and the physical shifting of signals occurring inthe package substrate, it is also possible to have the signals shiftedin the laminated board.

FIG. 4 illustrates a plurality of die-stacking modules 26 that areinterconnected to form a Package-On-Package 410. In one embodiment,eight die-stacking modules 26 may be stacked one on top of another toform a cube architecture, although any number of modules may be stackedwithout limiting the claimed features. It should be pointed out that thedie-stacking modules 26 are identical, and therefore, there is nodistinguishing feature to dictate the order of placement within thestack. In other words, the die-stacking modules 26 are interchangeable,one with another, within Package-On-Package 410.

FIG. 5 illustrates a bottom view of a memory cube, i.e., the bottom ofPackage-On-Package 410. As previously described, memory die have beenwire bonded and overmolded in a ball grid array package, then placed oneon top of another in a Package-On-Package technology. The chip enablesignal for the top die in the bottom module appears on solder ball 501.The top die's chip enable in the second module appears on solder ball502. This continues, with the chip enable for the top die in the thirdmodule appearing on solder ball 503, the chip enable for the top diefourth module appearing on solder ball 504, and the chip enable for thetop die in the fifth module appearing on solder ball 505, etc.

If each die-stacking module 26 included eight memory die, then eight CEsignals are electrically coupled to a separate solder ball, andtherefore, individually accessible. Thus, in the embodiment wherePackage-On-Package 410 includes eight die-stacking modules 26, thebottom view would have eight groups, where each group includes eight CEsignals. The shifting of the CE signals between the bottom solder ballsand the top lands in each die-stacking module 26 is the cubearchitecture having individual control of each memory die by theseparate CE signals applied to the corresponding solder balls. In otherwords, the CE connections that are daisy-chained through the cubearchitecture provide individual control of each memory die through thesolder balls at the bottom of Package-On-Package 410.

By now it should be apparent that embodiments of the present inventionallow increased memory storage efficiencies by using features of thepresent invention in die-stacking modules that are connected in aPackage-On-Package. By shifting of the CE signals the die-stackingmodule and daisy-chaining those signals through the Package-On-Package,individual control of each memory die is maintained.

While certain features of the invention have been illustrated anddescribed herein, many modifications, substitutions, changes, andequivalents will now occur to those skilled in the art. It is,therefore, to be understood that the appended claims are intended tocover all such modifications and changes as fall within the true spiritof the invention.

What is claimed is:
 1. An apparatus, comprising: a plurality of stackedmemory dice, at least some of the plurality of stacked memory diceincluding a Chip Enable (CE) signal connection electrically accessiblefrom a surface of a corresponding one of the stacked memory dice whilethe die is in the stack, each of the plurality of stacked memory dicehaving the CE signal connection being configured to be controlledindividually by a unique CE signal applied to the CE signal connection.